The present invention relates to a semiconductor IC (Integrated Circuit) device having a memory integrated therein, and more particularly to a technique having the effective application thereof to a semiconductor IC device in which a memory having a plurality of data transmission lines such as data input/output lines (I/O lines) and a logic circuit are integrated on the same semiconductor chip.
In recent years, the progress of LSI's (Large Scale Integrated circuits) to high integration has been made so that it is being possible to integrate a large-capacity memory and a large-scale logic circuit or operation circuit on a semiconductor chip of about 1 cm square. In such chips, a very high speed equal to or higher than 1 G byte/sec can be attained as the rate of data transfer between the memory and the logic circuit or operation circuit by making the number of I/O lines of the memory equal to or greater than several hundreds. Therefore, such chips are expected to, for example, the use thereof for image processing or the like in which high-speed data transfer for a memory is required.
A first prior art applicable to such a purpose of use includes, for example, DRAM (Dynamic Random Access Memory) macros disclosed by Toshio Sunaga, et al., "DRAM Macros for ASIC Chips", IEEE JOURNAL OF SOLID-STATE CIRCUIT, Vol. 30, No. 9, September 1995, pp. 1006-1014. This reference has disclosed an LSI chip which includes the combination of a logic and a DRAM macro of 288K-bit (32K.times.9 bits) capacity having 9 (nine) I/O lines fabricated by 0.8 .mu.m CMOS technique, and an LSI chip which includes the combination of a logic and a DRAM macro of 1.25M-bit (64K.times.18 bits) capacity having 18 (eighteen) I/O lines fabricated by 0.5 .mu.m CMOS technique.
As a second relevant prior art, U.S. Pat. No. 5,371,896 (issued Dec. 6, 1994) has showed a system in which a parallel computing system having many processors and memories coupled to each other is integrated on the same semiconductor chip. In this second prior art, a plurality of memories and a plurality of processors are integrated on the same semiconductor chip, and the memories and the processors are coupled by a network including crossbar switches. The second prior art is characterized in that an SIMD (Single Instruction Multi Data Stream) operation and an MIMD (Multi Instruction Multi Data Stream) operation can be performed in a changing-over manner, as required. At the time of SIMD operation, one of the plurality of memories is used as an instruction memory and the remaining memories are used as data memories. An instruction from the instruction memory is given to the processors in common with each other. At the time of MIMD operation, a part of the memories used as the data memories at the time of SIMD operation are used as instruction memories so that instructions from the separate instruction memories are given to the individual processors. Data transfer paths between the individual memories and the processors can be changed over to each other in various ways by the crossbar network.